Is this for NaN tagging, and can you use those bits without knowing the
float byte order? I presume if you store and retrieve the payload in the
same OS process the byte order stays constant so you don't need to care
about it. But the SRFI doesn't have a procedure to store a payload.
Originally it did, but you can't be sure that when a NaN is copied into a bytevector, you get the same payload bits that it originally contained, so that feature had to be abandoned.
The use of (endianness big) in the implementation is independent of the endianism of the processor; (endianness little) would do just as well, but the rest of the code would have to change.
Does toggling the byte order on bi-endian architectures affect the float
byte order as well, or does the FPU have its own byte order?
In almost all cases the byte ordering is the same nowadays, though some Arm32 processors always store the two words of a double-precision float in big-endian order even when the CPU is set to little-endian mode. On the PDP-11 and the Vax, the two 16-bit words of a single-precision float were likewise stored in big-endian order on a little-endian CPU.
Should it actually say 51 bits, since that seems to imply binary64 is
required?
Changed to say "the mantissa of nan other than the quiet/signaling bit".
It also uses "nan" in the prototype without properly defining what kind
of object it is. I assume it has to satisfy number? at least.
New wording says that an inexact real number that satisfies nan? is a NaN.
I can't answer for the authors' intentions, but I suspect that this SRFI
conflicts with NaN tagging. In such an implementation both +nan.0 and
something like a pair could be tagged as a NaN, but no object must
satisfy both pair? and number?, so some NaN payloads cannot be available
to the user.
Correct, which means they will never be returned to the user and therefore won't confuse these procedures. Ideally, nanboxing should only occupy the signaling NaN space and not the quiet NaN space, since 51 > 48 (the number of address bits in a 64-bit x86 or ARM architecture).
Indeed, where are the NaNs expected to come from?
Arithmetic procedures, which is to say FPU operations.